90 nm process
Semiconductor node that mainstreamed 300 mm wafers and 193 nm lithography.
Wikipedia / Wikimedia Commons
The 90 nm process is a semiconductor manufacturing node used to build integrated circuits. It followed the 130 nm node and was later succeeded by smaller nodes like 65 nm, 45 nm, and 32 nm. The name "90 nm" comes from a historical trend of scaling features by about 70% every two to three years, though the official designation was set by the International Technology Roadmap for Semiconductors (ITRS). Since at least 1997, process node names have been marketing terms with no direct relation to actual dimensions on the chip—neither gate length, metal pitch, nor gate pitch on a 90 nm device measures 90 nanometers.
The node was commercialized between 2003 and 2005 by companies such as Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments, and Micron Technology. A major shift at this node was the mainstream adoption of 300 mm wafers, replacing the previous 200 mm size. Many firms also introduced 193 nm wavelength lithography for critical layers, though not all did. This transition came with yield issues due to new photoresists, driving up costs.
Historically, a 90 nm silicon MOSFET was fabricated in 1988 at MIT by Iranian engineer Ghavam Shahidi (later an IBM director) along with D.A. Antoniadis and H.I. Smith, using X-ray lithography. Toshiba, Sony, and Samsung developed a 90 nm process between 2001 and 2002, introducing it in 2002 for Toshiba’s eDRAM and Samsung’s 2 Gb NAND flash memory. IBM demonstrated a 90 nm silicon-on-insulator (SOI) CMOS process in 2002, led by Shahidi. Intel demonstrated a 90 nm strained-silicon process that same year. Fujitsu commercially introduced its 90 nm process in 2003, followed by TSMC in 2004. Gurtej Singh Sandhu of Micron Technology began developing atomic layer deposition high-k films for DRAM, which helped lower costs for semiconductor memory starting with 90 nm node DRAM. Intel’s 90 nm process achieved a transistor density of 1.45 million transistors per square millimeter.
An example is Elpida Memory’s 90 nm DDR2 SDRAM process, which used 300 mm wafers, KrF (248 nm) lithography with optical proximity correction, 512 Mbit capacity, 1.8 V operation, and was derived from earlier 110 nm and 100 nm processes.
Processors built on 90 nm technology include Sony/Toshiba’s EE+GS (PlayStation 2), the Sony/Toshiba/IBM Cell Processor, IBM’s PowerPC G5 970FX, 970MP, and 970GX, the IBM “Waternoose” X
- introduced
- 2003–2005
- predecessor
- 130 nm process
- successor
- 65 nm, 45 nm, 32 nm processes
- wafer_size
- 300 mm (mainstream at this node)
- lithography
- 193 nm wavelength (introduced by many companies)
- transistor_density_example
- Intel 90 nm: 1.45 million transistors per square millimeter
- naming_basis
- Marketing, not related to actual dimensions
Lore & Background
A 90 nm silicon MOSFET was fabricated by Iranian engineer Ghavam Shahidi with D.A. Antoniadis and H.I. Smith at MIT in 1988 using X-ray lithography. Toshiba, Sony, and Samsung developed a 90 nm process during 2001–2002, introduced in 2002 for Toshiba's eDRAM and Samsung's 2 Gb NAND flash memory. IBM demonstrated a 90 nm silicon-on-insulator (SOI) CMOS process in 2002, led by Shahidi, and Intel demonstrated a 90 nm strained-silicon process the same year. Fujitsu commercially introduced its 90 nm process in 2003, followed by TSMC in 2004.
Reader's Guide
The 90 nm process represents a pivotal transition in semiconductor manufacturing, where the industry moved to 300 mm wafers and began adopting 193 nm lithography. This node enabled a wide range of processors, including Intel's Pentium 4 Prescott, AMD's Athlon 64 series, IBM's PowerPC G5, and the Cell processor used in the PlayStation 3. The node also saw the introduction of strained-silicon and SOI technologies, as well as high-k films for DRAM via atomic layer deposition. Despite being a marketing designation rather than a true measure of feature size, the 90 nm node was a workhorse for many companies from 2003 onward, supporting products from gaming consoles to servers. Its legacy includes the standardization of 300 mm wafers and the groundwork for subsequent nodes like 65 nm and 45 nm. The yield challenges and costs associated with new lithography and materials at this node foreshadowed the increasing complexity of later process generations.
Did You Know?
- A 90 nm silicon MOSFET was fabricated at MIT in 1988 using X-ray lithography by Ghavam Shahidi, D.A. Antoniadis, and H.I. Smith.
- The 90 nm node was the first where 300 mm wafers became mainstream, replacing the previous 200 mm diameter.
- Intel's 90 nm process achieved a transistor density of 1.45 million transistors per square millimeter.
- Since at least 1997, process node names have been purely marketing terms and do not correspond to actual gate lengths or pitches.
Frequently Asked Questions
What is the 90 nm process?
It is a semiconductor fabrication step used to build integrated circuits, sitting between the older 130 nm node and the smaller 65 nm generation that followed it. The node was officially designated by the International Technology Roadmap for Semiconductors rather than by any single company.
When did the 90 nm process hit the market?
Major chipmakers began shipping products built on this node roughly between 2003 and 2005. It was the generation that cemented 300 mm silicon wafers as the industry standard and brought 193 nm deep-UV lithography into widespread use across multiple foundries.
Does '90 nm' actually refer to a physical measurement on the chip?
No—by the time this node arrived, the number was essentially a marketing label inherited from an older era when it loosely matched feature sizes. Neither the gate length, metal pitch, nor gate pitch on a 90 nm part actually measures 90 nanometers.
How dense were transistors on a 90 nm chip?
Intel's 90 nm parts packed roughly 1.45 million transistors into each square millimeter of silicon. That density represented a substantial jump over the previous 130 nm generation and helped make more powerful processors affordable.
What came after the 90 nm process?
The industry moved on to 65 nm, then 45 nm, and eventually 32 nm nodes, each shrinking feature sizes further. The 90 nm generation served as the critical bridge that proved 300 mm wafers and 193 nm lithography could scale reliably before those smaller nodes arrived.
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